CAS: 108147-54-2; (2R,3S,4R,5S)-2-(Hydroxymethyl)Piperidine-3,4,5-Triol

上下游产品

1-脱氧野尻霉素 1,5-Dideoxy-1,5-Imino-D-Glucitol 19130-96-2
(3R,4S,5S,6R)-6-(羟基甲基)-2,3,4,5-哌啶四醇 5-Amino-5-Deoxy-D-Galactopyranose 107537-94-0
2,6-Di-O-Benzyl-1,5-Dideoxy-1,5-Imino-D-Galactitol 188779-02-4

1-脱氧野尻霉素置于palladium On Activated Charcoal 盐酸,Barium Dihydroxide,Sodium Hydroxide,氢气,Sodium Hydride,碳酸氢钠,Potassium Carbonate,对甲苯磺酸,溶剂黄146,三乙胺体系中,用 甲醇,二氯甲烷,水,N,N-二甲基甲酰胺,丙酮 用作溶剂,10.0~100.0 °C,350.0 Kpa 条件下,反应 163.0H,反应生成米加司他
参考文献:Synthesis Of D-Galacto-1-Deoxynojirimycin (1,5-Dideoxy-1,5-Imino-D-Galactitol) Starting From 1-Deoxynojirimycin
标题:Synthesis Of D-Galacto-1-Deoxynojirimycin (1,5-Dideoxy-1,5-Imino-D-Galactitol) Starting From 1-Deoxynojirimycin
摘要:
Doi:10.1016/0008-6215(90)80031-W

专利信息

专利号:US-2006293508-A1
优先权日:2005-06-08
标题:Stabilization of triflated compounds
发明人：MAJOR MICHAEL; PETERSON ROBERT; KOSINSKI SZYMON
权利人:MAJOR MICHAEL; PETERSON ROBERT; KOSINSKI SZYMON
摘要:Described are novel processes for the synthesis triflated sugars. These sugars are useful for the production of compounds, such as D-1-deoxynojirimycin (DNJ) and D-1-deoxygalactonojirimycin (DGJ). In particular, described is a multi-kilogram scale stabilization method for the synthesis of imino sugars.

专利号:US-5071990-A
优先权日:1989-11-01
标题:Preparation of intermediates and the synthesis of n-(2-hydroxyethyl)-2-hydroxymethyl-3,4,5-trihydroxypiperidines
发明人：HINSKEN WERNER
权利人:BAYER AG
摘要:A process for the preparation of N-(2-hydroxyethyl)-2-hydroxymethyl-3,4,5-trihydroxypiperidines of the formula ##STR1## which comprises reacting a compound of the formula ##STR2## with glyoxal of the formula ##STR3## in a solvent to give the addition product ##STR4## and reducing such addition product (II) with a hydrogen donor reducing agent to produce the intermediates of the formula and then the end product (I).

专利号:US-4189779-A
优先权日:1978-04-28
标 题:Parameter interpolator for speech synthesis circuit
发明人：BRANTINGHAM GEORGE L
权利人:TEXAS INSTRUMENTS INC
摘要:Disclosed is a parameter interpolator for a speech synthesis circuit. Using a parameter interpolator permits the data rate to the speech synthesis circuit to be lowered inasmuch as the incoming speech data is used to slowly charge the data previously inputted to the values of the incoming data. The speech synthesis circuit includes an input circuit for receiving the target values of the speech data and a memory for stored interpolated values of the speech data. The interpolator includes a circuit coupled to the input circuit and the memory which calculates the difference between the target values and the stored values. Another circuit is used to add a portion of the difference to the values stored in the memory; the particular portion of the difference is equal to 1/2N where N=0, 1, 2 . . . Further, the interpolator is arranged to inhibit the normal interpolation upon certain conditions, such as changes from voiced speech to unvoiced speech, and visa versa.

专利号:US-4234761-A
优先权日:1978-06-19
标题 :Method of communicating digital speech data and a memory for storing such data
发明人：WIGGINS JR RICHARD H; BRANTINGHAM GEORGE L
权利人:TEXAS INSTRUMENTS INC
摘要:A method of communicating Digital Speech Data to a speech synthesis circuit. The data is compressed to on the order of 1000-1200 bits, per second for normal human speech. The speech synthesis circuit utilizes linear predictive coding techniques for producing high quality speech or other sounds. The data is preferably stored in a memory which is coupled to the speech synthesis circuit. The data has variable frame lengths; in the disclosed embodiment, four different frame lengths are described having frame lengths from four bits to forty-nine bits. The memory stores the variable frame length data and communicates the same to the speech synthesis circuit in response to certain control signals.

专利号:US-4335275-A
优先权日:1978-04-28
标 题 :Synchronous method and apparatus for speech synthesis circuit
发明人：BRANTINGHAM GEORGE L
权利人:TEXAS INSTRUMENTS INC
摘要:A speech synthesis circuit capable of being implemented in an integrated circuit is disclosed. The speech synthesis circuit has an input port for receiving frames of data consisting of speech coefficients, a memory for storing interpolated values of the speech coefficients and an interpolator circuit coupled to the input port and to the memory. A synchronous timing circuit is provided for generating a data frame timing signal, interpolation count timing signals and parameter count timing signals. The rate of the parameter count timing signals is a multiple of the rate of the interpolation count timing signals, which is in turn a multiple of the rate of the data frame timing signal. These signals occur at predetermined times and are generated in the disclosed embodiment by Programmed Logic Arrays (PLA's). The data frame timing signal controls the receipt of a new frame of data at the input port. The interpolation count timing signal controls the initiation of a sequence of interpolations by the interpolator circuit between the values of the speech coefficients of the previous frame of data, and the values of the speech coefficients contained in the current frame. The parameter count timing signals are utilized to control when each coefficient is received at the input port after a data frame timing signal has occurred and also control the transferring of particular speech parameters to the interpolator circuit from the memory.

专利号:US-4304964-A
优先权日:1978-04-28
标 题:Variable frame length data converter for a speech synthesis circuit
发明人：WIGGINS JR RICHARD H; BRANTINGHAM GEORGE L
权利人:TEXAS INSTRUMENTS INC
摘要:A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero. The converter also detects the state of the repeat bit for controlling the synthesizing to use the coefficients received during the previous frame as the coefficient to be used to generate speech in response to the present frame. In this embodiment, when the repeat bit comes up, new pitch and energy parameters are inputted therewith. Further, the converters preferably detects particular codes in the energy parameter for determining when a pause occurs or when the last frame of data has been sent.